The constant efforts to improve the capture and power efficiency of digital videos have resulted in a huge range of image sensor research activities over the last decade. Better lithography and solid state technologies enable the production of higher resolution image sensors. Conventional serial-read-out technology requirements follow the same curve and get harder to design, so it seems inevitable that parallelism will be used in read-out schemes to relieve the analog-read-out circuits and maintain the same capturing speed. However, this transfer requires additional parallel ADC designs, mainly related to achievable precision, area and capacity. Cyclic ADC (CADC) 12-bit column parallel readings for CMOS image sensors is present in this work. The study's aim is to cover the architectures of multiple subcomponents of the CADC and to analyze the CADC's intermediate depth. A couple of different structures of the DAC multiplying (MDAC) were revised and a first-sign CADC design is to be performed using a 1.5- bit modified MDAC flip-over. Three comparator architectures and an interpolation of dynamic sub-ADCs are introduced.

Keywords : 12 Bit Cyclic ADC, CMOS Image Sensor, Column-Parallel Readout, MDAC, OTA.