In this current article 5- stage ring oscillator designed with lector technique for reduction in leakage power without increasing the propagation delay. a lector technique to used two LCT transistor in which one of ptype and another one is n-type at each stage of ring oscillator and LCT is manage by source of second LCT transistor. In this current article is simulate and compare the various parameter are power dissipation, frequency, average power of 5- stage ring oscillator based CMOS as well as CNT at 32nm transistor based technology with the help of lector technique then comparison CNT based transistor better result display as compare to the CMOS based transistor using SPICE simulation tools.

Keywords : CMOS, carbon nano tube (CNT), lector, leakage power, leakage current