This paper is handling the problematics of implementation of selected cryptography algorithms in symmetric and asymmetric category, specifically RSA in symmetric and DES in asymmetric field. The implementation is focused on representation of computer unit, which is decelerated as hardware accelerator. Chapters are divided from the introduction to problematics to description of algorithms DES and RSA, that are the part of computer security field, the tested FPGA device is described in its own chapter, the design and completed solution and the results of systematic tests has presence at the end of this document.

Keywords : RSA; Computer Security; DES; Hardware Description Language; FPGA; VHDL.